Top Wafer Cleaning Equipment Companies - MarketsandMarkets

The Wafer Cleaning Equipment Market is expected to reach USD 16.5 billion by from USD 10.1  billion in , at a CAGR of 10.4% during the – period.

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The major players in the Wafer Cleaning Equipment Market with a significant global presence are include SCREEN Holdings Co., Ltd. (Japan), Tokyo Electron Limited (Japan), Lam Research Corporation (US), Applied Materials Inc, Inc. (US), Shibaura Mechatronics Corporation (Japan), Akrion Technologies (US), Modutek.com (US), PVA TePLA AG (Germany), Entegris (US), ULTRON SYSTEMS, INC. (US), Veeco Instruments Inc. (US), SEMES (South Korea), AXUS Technology (US), Beijing TSD Semiconductor Equipment Co., Ltd. (China), Toho Kasei Co., Ltd. (Japan), Cleaning Technologies Group (US), SEMETEK (US), AP&S International GmbH (Germany), ITW (US), RENA Technologies GmbH (Germany), TDC Co., Ltd. (Japan), Orbray Co., Ltd. (Japan), DAINICHI SHOJI K.K (China), and Ultra t Equipment Company Inc. (US).

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SCREEN HOLDINGS CO., LTD.:

SCREEN Holdings Co., Ltd. (SCREEN) is an international technology corporation renowned for its expertise in creating and delivering cutting-edge solutions across the domains of semiconductors, displays, and printed circuit boards (PCBs). SCREEN offers advanced semiconductor manufacturing equipment for integrated circuit production. Its equipment encompasses processes like lithography, etching, cleaning, thermal processing, and wafer inspection. SCREEN is one of the dominant players in the wafer cleaning equipment market. The company operates primarily through the following reportable business segments: Semiconductor Production Equipment business (SPE), Graphic Arts Equipment business (GA), Display Production Equipment and Coater business (FT), and PCB-related Equipment business (PE). SCREEN offers wafer cleaning equipment under its SPE business segment. Through the SPE business segment, SCREEN also offers coat/develop tracks, annealing systems, measurement systems, inspection systems, direct imaging systems for advanced packaging lithography, and wafer cleaning systems.

TOKYO ELECTRON LIMITED:

Tokyo Electron Limited () is a renowned Japanese company that plays a pivotal role in the semiconductor and flat-panel display industries. The company offers industrial electronic products that include semiconductor manufacturing machines, flat panel display (FPD) manufacturing machines, photovoltaic (PV) manufacturing machines, and electronic components. is the key player in the wafer cleaning equipment market. The company operates primarily through two reportable business segments: Semiconductor and Production Equipment, and FPD Production Equipment. The Semiconductor and Production Equipment segment, which comprises Wafer Cleaning Equipment as a subsegment, is the dominant segment that provides the majority of products such as coaters/developers, etch systems, wafer edge trimming systems, deposition systems, SiC Epitaxial CVD system, test systems, others.

The company’s key subsidiaries include Tokyo Electron Technology Solutions Ltd. (Japan), Tokyo Electron Kyushu Ltd. (Japan), Tokyo Electron Miyagi Ltd. (Japan), Tokyo Electron US Holdings, Inc. (US), Tokyo Electron Europe Ltd. (UK), Tokyo Electron Korea Ltd. (South Korea), and Tokyo Electron Taiwan Limited (Taiwan).

LAM RESEARCH CORPORATION:

LAM Research is one of the leading players of semiconductor manufacturing equipment. It is involved in the manufacturing and servicing of majorly front-end wafer manufacturing equipment. The company offers thin film deposition, plasma etch, photoresist strip, and wafer cleaning. It is one of the early-stage giants, allowing chipmakers to build smaller, faster, and better performing electronic devices. The company operates through two reportable business segments: Systems revenue and Customer-support related revenue and other.

The company mainly focuses on spending extensively on R&D activities to foster product innovation and development. Lam research Corporation offers extensive array of cutting-edge solutions tailored to different phases of semiconductor manufacturing. Its offerings include plasma etch systems, chemical vapor deposition (CVD) systems, atomic layer deposition (ALD) systems, physical vapor deposition (PVD) systems, and advanced wafer cleaning equipment.

APPLIED MATERIALS, INC.:

Applied Materials, Inc. offers a comprehensive range of manufacturing equipment, services, and software designed for application in the semiconductor, display, and related industries. It is a key player in the wafer cleaning equipment market. It offers semiconductor products, roll-to-roll coating systems, solar products, large area deposition systems for LCD and OLED displays, along with smart factory semiconductor packaging and automation software solutions.

Applied operates in four reportable segments: Semiconductor Systems, Applied Global Services, and Display, Adjacent Markets, and corporate and other. Applied Materials offers wafer cleaning equipment, such as rapid etch, thermal processing, semiconductor capital equipment, under its Semiconductor Systems business segment. These equipment’s find applications in the deposition, chemical mechanical planarization, ion implantation, metrology and inspection, and wafer packaging.

The company’s manufacturing plants and sales offices are located in China, South Korea, Taiwan, Japan, Southeast Asia, US, and Europe. Additionally, the company also focuses extensively on R&D activities to foster product innovation and development.

ENTEGRIS:

Entegris, Inc. is actively involved in the development, production, and distribution of specialized materials tailored for the microelectronics sector. The company operates through distinct business segments, including Specialty Chemicals and Engineered Materials (SCEM), Advanced Materials Handling (AMH), and Microcontamination Control (MC), and Advanced Planarization Solutions (APS). Within these segments, Entegris delivers purity process chemistries, gases, and materials, along with sophisticated delivery systems, to support cutting-edge manufacturing processes in the semiconductor and advanced industries. The AMH segment focuses on creating solutions for monitoring, safeguarding, transporting, and supplying crucial liquid chemistries and substrates across a wide spectrum of applications, especially in the semiconductor domain. Additionally, the MC segment provides remedies to enhance the purity of essential liquid chemistries and gases, both of which are pivotal in semiconductor manufacturing and other high-technology fields.

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Wafer Cleaning Equipment Market by Equipment Type (Single-wafer Spray System, Batch Spray Cleaning System, and Scrubbers), Application, Technology, Operation Mode, Wafer Size (Less than Equals 150 mm, 200 mm, 300 mm) and Region - Global Forecast to

A dislocation is created when there is sufficient stress to break silicon bonds and displace silicon atoms from their normal locations. This can occur during IC fabrication due to built-in device stress, as when oxide presses against a trench sidewall or when a high concentration of small boron atoms is implanted into a volume adjacent to a volume containing larger atoms. Or dislocations can be created when furnace slip takes place due to an excessive across-the-wafer temperature nonuniformity.

The dislocation is both a structural and an electrical defect. The tube-like opening down one side of a dislocation line can act as a diffusion pipe, accelerating and channeling the diffusion of dopant atoms and producing an IC device that is shorted or that breaks down at a low voltage. The electrical properties of a dislocation can cause several types of electrical failures because a dislocation promotes recombination, conduction, and generation.

If a dislocation is present in the base of a transistor, it decreases the gain because it acts as a trap and accelerates the recombination of minority charge carriers. The dislocation line is a conductive path, and the path becomes even more conductive when metal impurity atoms become attached to the silicon atoms along the dislocation. If a dislocation ends under a gate oxide, its enhanced conductive properties can cause gate oxide integrity failure.

The most common dislocation-induced failure mechanism is leakage. For an IC device to function properly, it must be possible to effectively change the silicon into an insulator by creating a depletion region. Conduction in an MOS transistor is turned off by applying a potential to the gate to create a depletion region by pushing the majority charge carriers out of the channel. A reverse-biased P/N junction prevents current flow because the reverse bias separates the holes and electrons and creates a depletion region at the junction. However, if a dislocation threads from one electrode, through a depletion region, to another electrode, then conduction along the dislocation line causes current to flow when it should not. This is one form of dislocation-induced leakage. Leakage also occurs when a dislocation within the depletion region acts as a line of generation centers, converting thermal energy into electron-hole pairs. The electric field within the depletion region causes the electrons to flow in one direction and the holes to flow in the other direction, and this constitutes the flow of a leakage current.

Whether or not a dislocation actually causes an IC device failure depends on where the dislocation is located. If the dislocation comes up under a field oxide, for example, it does no harm. But if it threads through a P/N junction, it can cause a leakage failure. If a wafer has a high incidence of leakage failures, failure analysis can be carried out by stripping off the IC pattern layers and applying a defect etch to the silicon surface (Fig. 1). Dislocation etch pits then show where the dislocations intersected the silicon surface. If the dislocation etch pits show no across-the-wafer pattern, but are consistently located at certain IC device structures, then the stress that created the dislocations was probably built-in device stress (Fig. 2). But if the dislocations are concentrated in a center spot (Fig. 3 & 4) or an edge pattern, then the stress that created the dislocations was probably furnace stress. Often a leakage failure map will suggest whether or not furnace slip has taken place. If wafer failure analysis shows a spatial correlation between a high dislocation density and a high leakage failure rate, then you can be virtually certain that it was the dislocations that caused the leakage.

Wafer surface after pattern removal and defect etching. Short shallow dislocation loops are consistently located at certain IC device structures. This indicates that the dislocations were probably produced by built-in device stress.

Wafer surface after pattern removal and defect etching. Dislocation etch pits are located along slip lines. This indicates that the dislocations were produced by a nonuniform temperature distribution during furnace processing.

Leakage failure map. This "four corners" leakage failure pattern for a <100> wafer indicates that the wafer probably slipped at the edges due to too-rapid edge-first heating during furnace processing.

Leakage failure map. This "center spot" leakage failure pattern indicates that the wafer may have slipped in the center due to too-rapid edge-first cooling during furnace processing.

The Control of Oxygen Precipitation and the Impact of Internal Gettering

Vacancy concentration profiles result in ideal precipitation for gettering.

• Controlling oxygen behavior in silicon wafers via vacancy profiles is more cost-effective than conventional out-diffusion and renucleation methods.
• Proper vacancy programming forces the wafer to behave in a specific wa
• The vacancy-based approach greatly simplifies the use of silicon by decoupling the formation of the IG structure from the details of the thermal process used in device fabrication.

Controlling oxygen behavior in silicon is undeniably one of the most important challenges in semiconductor materials engineering. In particular, control of oxygen precipitation is essential for the development of internal gettering (IG) in IC manufacturing. Gettering schemes play an important role in yield management in IC manufacturing. In the 20 or so years since the discovery of the IG effect silicon wafers, many scientists and engineers have struggled with the problem of precisely and reliably controlling the precipitation of oxygen that occurs in silicon during the processing of wafers into integrated circuits. This has met with only partial success, in the sense that the “defect engineering” of conventional silicon wafers is still an empirical exercise. It consists largely of careful, empirical tailoring of wafer type (oxygen concentration, crystal-growth method, and details of any additional preheat treatments, for example) to match the specific process details of the application to which the wafers are submitted, in order to achieve good and reliable IG performance.

Reliable and efficient IG requires the robust formation oxygen-precipitate-free surface regions (“denuded zones”) and a bulk defective layer consisting of a minimum density(1) (at least about 108cm-3) of oxygen precipitates during the processing of the silicon wafer. Uncontrolled precipitation of oxygen in the near-surface region of the wafer represents a risk to device yield. The basis of the conventional method for dealing with the creation of this layered structure has been to ensure sufficient outdiffusion of oxygen from the near-surface region in order to suppress nucleation and growth. In recent years, due to radical reductions in the total thermal budgets of processes that make submicron devices, this method is no longer cost-effective.

It is possible to install vacancy-concentration profiles into silicon wafers that result in the ideal precipitation performance for IG purposes. Such an ideal vacancy profile means a high vacancy concentration in the wafer bulk and proper vacancy depletion in the near-surface region. The installation of controlled concentration profiles of vacancies is now a wafer-manufacturing process, as depicted in Figure 1. While a high concentration of vacancies enhances oxygen clustering, there is a lower bound on vacancy concentration below which clustering is “normal”. This is quite a sharp transition and lies around 5Xcm-3. Thus a profiled vacancy concentration allows for the programming of “layered” structures — exactly what is required for the effective engineering of structures by IG. This is the basis underlying the “Magic Denuded Zone” (or MDZ) wafer.(2) A schematic illustration of this new materials-processing technique is shown in Figure 2. The use of such a vacancy-based approach greatly simplifies the use of silicon by decoupling the formation of the IG structure from the details of the crystalgrowth process, the oxygen content of the wafer, and the details of the thermal process used to fabricate the device in question.

The Installation of Vacancy-Concentration Profiles in Silicon Wafers

The installation of appropriate vacancyconcentration profiles in silicon wafers is a nthree-step process, but all steps occur in a single rapid thermal processing (RTP) run.(2)

1. When silicon is raised to high temperatures, vacancies and interstitials are spontaneously produced in equal amounts through Frenkel pair generation, a very fast reaction. At distances far removed from crystal surfaces, we thus have CI = Cv = {CIeq (T)Cveq(T)}1/2, where T is the process temperature. If the sample were to be cooled at this point, the vacancies and interstitials would mutually annihilate each other in the reverse process of their generation.
2. In wafers, however, the surfaces are not far away, and this situation changes very rapidly. Equilibrium boundary conditions (not oxidizing or nitriding) lead to coupled fluxes of interstitials to the surface and vacancies from the surface because CIeq(T) < Cveq(T), and because of the rapid establishment of equilibrium conditions throughout the thickness of the wafer. Experiments suggest that this occurs in a matter of seconds or less. This equilibration is primarily controlled by the diffusivity of the fastest component, the self-interstitials, since the concentrations are roughly equal.
3. Upon cooling, two processes are important: direct recombination of vacancies and interstitials, and diffusion of interstitials toward the surfaces. In the wafer bulk, the slower vacancies are now the dominant species of the coupled diffusion, and hence the equilibration process at the surface is not as fast as the interstitial-dominated initial equilibration. It is thus possible to “freeze-in” excess bulk vacancies at not-unreasonable cooling rates (ca. 50- 100°C/s). The residual bulk concentration of vacancies following recombination with interstitials, Cv, is the initial difference of Cveq - CIeq (at the process temperature T). Closer to the surfaces, Cv is lower, due to out-diffusion (again, primarily controlled by the dominant vacancies) toward the decreasing equilibrium values at the wafer surface. The level of bulk precipitation is controlled by the process temperature, through Cveq - CIeq, while the depth of the denuded zone is controlled by the cooling rate, through the diffusion of vacancies during cooling.

By installing a given precipitate profile into a silicon wafer, we have effectively programmed it to behave in a certain way. The precipitate profiles that result from the vacancy-programming such as is illustrated in Figure 2 produce perfect internal gettering performance reliably and reproducibly.

The denuded, or oxygen precipitate free, zone in MDZ® is a real one in the sense that the near surface density of oxygen precipitates is effectively zero. In other approaches to the problem this is not necessarily the case. For example, when oxygen precipitation enhancement is attempted at the crystal growth level, as in the case of nitrogendoped silicon, no "real" denuded zones are possible. The high temperature oxygen out-diffusion treatments which are applied to such wafers result in an "apparent" denuded zone only. The grown-in precipitates are not themselves dissolved. The oxygen concentration reduction near the surface merely restricts the size of precipitates there; at some point they cannot be detected by simple etching. But the density of oxygen related defects, in fact, remains the same -- all the way to the wafer surface. Crystal-growth based precipitation enhancement schemes increase the constraints placed on the crystal growth process. MDZ® frees the crystal growth process to be whatever it needs to be to decrease costs.

The precipitate structure is dictated by the vacancy concentration profile installed in the wafer. Proper vacancy programming forces the wafer to behave in an ideal way. It does not matter what the oxygen content of the wafer is. It does not matter what the crystal growth process was that produced the wafer -- the MDZ® process erases the crystal-history of the wafer. From an IC manufacturer's point of view, a single, highly simplified specification can now cover a multitude of applications and product ranges, hugely simplifying their use and increasing flexibility.

References:

• R. Falster, G.R. Fisher, and G. Ferrero, Appl. Phys. Lett. 59 () p. 809.
• R. Falster, D. Gambaro, M. Olmo, M. Cornara, and H. Korb, in Defect and Impurity Engineered Semiconductors and Devices II, edited by S. Ashok, J. Chevallier, K. Sumino, B.L. Sopori, and W. Götz (Mater. Res. Soc. Symp. Proc. 510, Warrendale, PA, ) p. 27.
• R. Falster and V.V. Voronkov, “The Engineering of Intrinsic Point Defects in Silicon Wafers and Crystals”, Mater. Sci. Eng., B 73 () p. 69.

Magic Denuded Zone®, MDZ®, and the MDZ logo are registered trademarks of GlobalWafers. All rights reserved. The MDZ process is protected by US patent 5,994,761 and other patents worldwide.

<100> Notch Orientation for Increased PMOS Drive Current

Benefits and Features:

• PMOS Ion increases by 10-20%
• No degradation in NMOS
• No fab integration issues or process changes are needed... wafer is still (100) surface orientation
• Applicable to multiple platforms including standard bulk wafers, SOI, and strained wafers

CMOS transistor scaling progress has been enabled by continuous reductions in channel length and gate dielectric thickness. In the sub-100nm MOSFET transistor scaling regime, fundamental limits in channel length and gate dielectric scaling are being encountered. The primary barriers to continuing scaling of planar CMOS transistors are short channel effects (SCE), which are increasingly limiting the transistor drive current improvement, and leakage current through the very thin gate dielectric. In order to manage SCE, the channel doping continues to increase. But, increasing the channel doping degrades mobility by introducing more charged impurity scattering sites. Also, the future implementation of high-K gate dielectric for control of gate leakage is known to degrade channel mobility. Because MOSFET drive current also depends on the mobility of charge carriers in the channel of the device, enabling a mobility enhancement in the device channel can offer a means to offset the negative aspects of managing SCE and gate leakage. Mobility, which describes the ease in which charge carriers drift in a semiconductor, is inversely proportional to carrier mass. Enhancing mobility (µ) enables higher MOSFET drive current which leads to higher device speed as described by the functional relationships shown below.

You will get efficient and thoughtful service from Microtreat.

Mobility enhancement methods are the subject of an intense investigation at the starting wafer level and in the device fabrication process. The main approaches for enhancing mobility at the starting wafer level are by changing the orientation of the wafer notch, changing the wafer surface orientation, and straining the device channel. Table 1 highlights the mobility enhancement options available at the starting wafer level. The change in notch orientation from <110> to <100> is a drop-in solution that enables a 10-20% enhancement in PMOS operating current.

Several studies published in scientific literature demonstrate that orienting the PMOS channel along the <100> direction on (100) surface orientation wafers results in a gain of 10-20% in the transistor drive or “on current”(1-3). No degradation has been observed on NMOS transistors. The re-orientation of the channel directions is more easily realized by changing the starting wafer than by modifying the transistor layout methodology. The mechanism for the gain in PMOS drive current is increased mobility due to the reduction in the effective mass of holes moving along the <100> direction.

Orienting the channel direction along <100> is a simple process change in the starting wafer fabrication. Historically, the wafer flat or notch on (100) surface orientation wafer has been formed along the <110> direction at crystal grinding because these directions define the easily cleaved crystal directions of a (100) surface orientation wafer. However, since wafer dicing is done by sawing through the scribe lines orienting along <110> is no longer a technological requirement. Figure 1 shows the simple process change for rotating the crystal piece by 45 degrees at crystal grinding in order to form the wafer notch or flat along the <100> direction.

The orientation of the CMOS channel along the <100> direction offers a simple, low cost, low risk production proven enhancement of the PMOS transistor with no degradation to the NMOS transistor or complications in device process integration. It can be applied to all starting material platforms including advanced polished wafers, epitaxial wafers, and SOI wafers. The <100> notch option is already a high volume wafer fabrication process. It is a production proven starting wafer option for enhancing the performance of sub-100nm CMOS technologies. Beyond the CMOS applicability described in this note, the reorientation of the notch position to <100> has also been reported to enable improvement in the DRAM deep trench capacitor shape profiles etched into the silicon substrate, increasing cell capacitance by ~ 25%(4).

References:

• R. Khamankar et al., Symposium on VLSI Technology Digest of Technical Papers, pg 162.
• T. Matsumoto et al., IEDM Digest of Technical Papers, pg 663.
• T. Komoda et al., IEDM Digest of Technical Papers, pg 217.
• J. Amon et al., IEDM Digest of Technical Papers, pg 73.

Measurement of Interstitial Oxygen in Silicon Ingots

Increased customer confidence in process control and product capability

Benefits and Features:

• Measurement technique increases customer confidence in overall process control and product capability.
• Increases efficiency and accuracy of oxygen measurements in silicon ingots.
• Allows rapid feedback to crystal engineers in the crystal pulling area.
• Whole rod FTIR performance was demonstrated through direct correlation to conventional FTIR measurements.

Description:

Interstitial oxygen content of a silicon wafer is an important material characteristic for most modern device technologies. Interstitial oxygen in silicon is typically measured by infrared absorption using either 2 mm thick slugs or thinner product wafers. The accuracy of these measurements is subject to error. These wafer measurements are time consuming and potentially introduce handling damage or contamination to the finished polished wafer. A new infrared approach allows the measurement of interstitial oxygen in single crystal silicon. Ground, large diameter, silicon crystals are profiled for interstitial oxygen using a Fourier transform infrared (FTIR) spectrometer transmitting through full diameter crystals. Measurement intervals and sample sizes may be defined prior to the wafering process, improving assurance of product quality and allowing rapid feedback to the crystal pulling floor. Wholerod FTIR (WRFTIR) measurements can increase the producer and consumer confidence in overall process control and product capability, efficiently generating oxygen profiles along the crystal.

Technical Details:

Interstitial oxygen content of a silicon wafer is an important material characteristic for most modern device technologies.(1) Strengthening and contamination gettering properties of properly specified interstitial oxygen in silicon and their relationship to device performance are well understood and published.(2) Oxygen is incorporated in the silicon lattice during the growth process by dissolution of the quartz crucible.

Interstitial oxygen in silicon is typically measured by infrared absorption using either 2 mm thick slugs or thinner product wafers.(3,4) The accuracy of these slug or wafer measurements is subject to error unless both sample surfaces are polished, creating a more predictable optical transmission and internal reflection condition.(5) In addition, the crystal-pulling engineer may not fully understand the oxygen variation of the process unless most of the wafers are measured and the crystal oxygen profile is reassembled in a database. These wafer measurements are time consuming and potentially introduce handling damage or contamination to the finished polished wafer.

A new infrared approach allows the measurement of interstitial oxygen in single crystal silicon. Ground, large diameter, silicon crystals are profiled for interstitial oxygen using a Fourier transform infrared spectrometer transmitting through full diameter crystals.(6) Measurement intervals and sample sizes may be defined prior to the wafering process, improving assurance of product quality and allowing rapid feedback to the crystal pulling area. Whole-rod FTIR (WRFTIR) measurements will increase the producer and consumer confidence in overall process control and product capability, efficiently generating oxygen profiles along the crystal (Figure 1).

Measurement Principles:

Routine measurement of interstitial oxygen in silicon wafers utilizes infrared absorption at cm-1 (9.03 µm). This is the absorption band associated with anti-symmetric vibration of SiO2 in the silicon lattice.(7) The infrared beam passes through a wafer sample from the front to the back (Figure 2). An absorbance spectrum of an oxygen-free, float zone reference sample is “subtracted” from the sample spectrum to remove interference from multiplephonon excitations of silicon near that band. Commercially available FTIR systems simulate the subtraction process in various ways for rapid measurement of the oxygen content. Quantitative evaluation of interstitial oxygen in wafers also requires accurate understanding of the measurement effects of sample thickness, surface finish, and dopant concentration. Dopant atoms like boron or phosphorus absorb infrared light and limit the usable range of infrared analysis.(8)

In the WRFTIR method, an infrared beam passes through a full crystal diameter, shown in Figure 1. The resulting absorbance spectrum represents the average interstitial oxygen content through one crystal diameter. This measurement uses a less intense, cm-1 (5.81 µm) absorption band that is a re-occurrence of the cm-1 band in silicon.(9,10)

Although interference from multiple-phonon excitations of silicon is negligible near the cm-1 band, the band intensity is too low to be useful in wafer measurements. When measuring through a large diameter silicon crystal, however, the cumulative absorbance is enough to provide a strong measure of interstitial oxygen content with little interference.

No measurement is possible in a full diameter crystal using cm-1 light because almost none of it passes through the whole crystal. Likewise, absorption at cm-1 is too weak to provide a measurable absorption peak when the path length is a wafer thickness (Figure 3). A long path length with low absorption provides a good combination for accurate WRFTIR measurements.

Instrumentation:

GlobalWafers has developed specifications for a WRFTIR system over the past few years. BioRad Laboratories further refined and fabricated the system and sells it as the QS-FRS. The instrument employs a standard 300 series optical bench mounted on a rail assembly. A mercury cadmium telluride (MCT) detector was selected for its excellent response and sensitivity characteristics.

The system is capable of measuring up to five crystal segments with a total length of 1.8 meters. These crystals remain fixed as the FTIR measures a specific point, processes data and moves to the next specified point. Collection conditions and spatial frequency of data along the crystal length are operator controlled. Instrument software allows definition of resolution, collection time, calibration, and spacing among adjacent measurement locations.

Experiment Design:

WRFTIR performance was demonstrated through direct correlation to conventional, wafer FTIR measurements. Sixteen p-type and four n-type, 200 mm diameter silicon crystals were selected to create a range of resistivity and oxygen values. The resistivity of the crystals ranged from 3.1 ohm-cm n-type to 56 ohm-cm p-type with the corresponding dopant density of 3. to 2. atoms per cm3. The interstitial oxygen ranged from 11 to 17 ppma (ASTM F). Of these twenty crystals, growth controls for four crystals were intentionally altered to create large oxygen variations along the crystal length (Figure 4). These profile variations provided a natural dispersion in the data to be discriminated by the two methods. The fulllength crystals were cut to usable lengths and ground to a nominal, 200 mm diameter.

Crystals were measured at 5 mm increments along the length and repeated twice at each defined measurement location. A single WRFTIR measurement was based on 64 scans of the FTIR mirror to calculate the absorbance spectrum. The ground crystals were subsequently processed into double side polished wafers. Wafer samples were selected at 50 mm intervals along the crystal and measured for interstitial oxygen with conventional FTIR techniques. Calibration of the WRFTIR and the conventional FTIR was performed with certified NIST traceable standards.

Three different 200 mm products were selected by resistivity specifications to support a confirming production experiment. Wafer oxygen distributions, measured on random samples using conventional FTIR techniques, were compared to “simulated distributions” derived through WRFTIR analysis.

Results and Discussion:

Exact positions from the WRFTIR oxygen profile have been compared to corresponding double-side polished wafers selected from the crystals and measured by conventional methods. Excellent agreement was achieved between the WRFTIR and double-side polished wafercenter oxygen shown in Figure 5, shown on the next page. The red points correspond to high resistivity (low doping) samples, and the blue points correspond to low resistivity (high doping) samples. Clearly, free carrier absorption interferes with the oxygen measurement. Wafer radial oxygen variation, considered to be a potential source of interference, is insignificant for typical oxygen gradients produced today.

Regression statistics were calculated for various subsets of the data set to demonstrate the magnitude of carrier concentration interferences. Various regression combinations of resistivity subsets (all, high or low) and wafer oxygen radial gradient subsets (all, <2% or >2%) are provided in Table 1. Each regression analysis combining high and low resistivity subsets demonstrates significantly higher standard error. Only slight degradation in correlation occurs in cases that include oxygen gradients greater than 2%.

These correlation results suggest that accurate WRFTIR calibration is possible for predicting wafer center oxygen. At least two calibration options are required to assure accuracy over the normal working resistivity range. Additional WRFTIR calibration factors or algorithms for carrier concentration may be applied if subsequent testing suggests a need.

Conclusion:

Average interstitial oxygen can accurately be measured in full diameter, 200 mm silicon crystals using the cm-1infrared absorption band. The technique provides the crystal engineer rapid feedback for continuous process improvement and control. The method gives an increased understanding of the complete oxygen distribution. Accurate calibration to NIST certified standards and routine use of the WRFTIR has been demonstrated with minimal interference from radial oxygen gradient and predictable interference from resistivity over a wide range of product specifications.

Acknowledgments:

We gratefully acknowledge the contributions to this work from R. Prasad Dasari and K. Krishnan of BioRad. Portions of this article was published in the June issue of Semiconductor International. We would like to thank them for allowing us to reproduce portions of the article for this Applications Note.

References:

• J.C. Mikkelsen, JR., Material Research Society Symposium Proceedings, Vol. 59, pp. 19-30, .
• F. Shimura (ed), Oxygen in Silicon, Academic Press,
• Hidenobu Abe, Isamu Suzuki, and Hiroshi Koya, “The Effect of Hydrogen Annealing on Oxygen Precipitation Behavior and Gate Oxide Integrity in Czochralski Si Wafers,” J. Electrochem. Soc., Vol. 144, No.1, pp. 306-310, .
• K. Krishnan, Material Research Society Symposium Proceedings, Vol. 83-9, pp. 285-292, .
• L. Koster, and F. Bittersberger, Material Research Society Symposium Proceedings, Vol. 262, pp. 271- 276, .
• Joseph C. Holzer, Harold W. Korb, and Klaus Drescher, Unites States Patent #5,550,374, GlobalWafers, .
• Bernard Pajot, and Bernard Cales, Material Research Society Symposium Proceedings, Vol. 59, pp. 39-44, .
• F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, Inc. , pp 228-233, .
• B. Pajot, H.J. Stein, B. Cales, C. Naud, “Quantitative Spectroscopy of Interstitial Oxygen in Silicon,” J. Electrochem. Soc., Vol. 132, No.12, pp. -, .
• John R. Ferraro and K. Krishnan, Practical Fourier Transform Infrared Spectroscopy, Academic Press, Inc., pp. 296-328, .
• Bio-Rad Semiconductor Division, 237 Putnam Avenue, Cambridge Massachusetts , U.S.A.

The crystal becomes an "ingot" only after the seed-end (the top) and the tapered-end (the bottom) are removed using an inner-diameter (ID) saw. These ends are sometimes discarded; however, to avoid a complete material loss, some ends are re-melted and used in future crystal specifications. After the ends are cut-off, the ingot is cut into shorter sections in order to optimize the slicing operation that will follow later. Next, each section is ground to the specified diameter on a mechanical lathe. A thick "slug" is taken at the end of each ingot for quality control and testing. This includes measurement of resistivity, oxygen, carbon, and bulk defects. The whole ingot is then x-rayed to confirm crystal (atomic structure) orientation.

Following x-ray, the ingot is mounted on a carbon "block" using an epoxy resin. It is carefully mounted according to its orientation. The resin is allowed to cure before the ingot proceeds to slicing.

Silicon wafers are sliced from the ingot using both ID and Wire type saws. The ID saw can produce only single wafers at a time. The Wire saws are more efficient because we are able to slice the entire ingot at once. After the epoxy has cured, the ingot section is inverted and mounted into the 10-ton Wire saw. The ingot is gradually lowered into a "web" of fast moving, ultra-thin wire. The cutting action is created by pouring an abrasive slurry on the wire web, which is actually a single wire being fed from one spool to another. Immediately after slicing, the "as-cut" wafers are cleaned in a series of chemical baths to remove any residual slurry. From here, the wafers proceed into a series of refining steps to make them stronger and flatter.

First, the sharp, fragile edges are rounded or "profiled" to provide strength and stability to the wafer. This will ultimately prevent chipping or breakage in subsequent processing. Next, each wafer is laser-marked with very small alphanumeric or bar code characters. This laser-mark ID gives full trace-ability to the specific date, machine, and facility where the wafers were manufactured. The wafers are then loaded into a precision "lapping" machine that uses pressure from rotating plates and an abrasive slurry to ensure a more uniform, simultaneous removal of saw damage present on both front and backside surfaces. This step also provides stock removal and promotes flatness uniformity - a critical foundation for the polishing manufacturing process.

Now the wafers must go through an "etching" cycle. Chemical etching is necessary for the removal of residual surface damage caused by lapping; it also provides some stock removal. During the etching cycle, wafers progress down another series of chemical baths and rinse tanks with precise fluid dynamics. These chemical solutions produce a flatter, stronger wafer with a glossy finish. All wafers are then sampled for mechanical parameters and for process feedback.

A

Å -- Angstrom
A-defects -- Dislocation loops in Silicon formed by agglomeration of interstitials
AA -- Atomic absorption
AE -- Acid Etch
AFM -- Atomic Force Microscopy
ALCVD -- Atomic Layer Chemical Vapor Deposition
AMC -- Barrel or batch type Epi reactor (Applied Materials)
APCVD -- Atmospheric-Pressure Chemical Vapor Deposition Furnace
ASIC -- Application Specific Integrated Circuit
ASM -- a single-chamber Epi reactor (ASM America)
ASTM -- American Standard Test Method
ASTM -- American Society for Testing and Materials
Acceptor: (p-type wafer) an impurity, as Gallium, Boron, etc., whose atoms in a semi-conductor produce positive, mobile charges while remaining bound in the crystal structure with a unit negative charge.
Acid: Any compound that can react with a base to form salt. Used mainly in Etching and Cleaning stages.
Alloy: Mixture of metals to increase durability.
Ambient: Natural state of the environment.
Ambient light: Normal room lighting.
Angle of Incidence: Angle in which the light goes into the wafer.
AOG: Axial Oxygen Gradient. Profile of oxygen concentration along the length of a crystal.
Argon: Inert, colorless, odorless gas used as the growing atmosphere in the crystal puller chamber; argon is backfilled after air purge.
Atmosphere: Standard barometric pressure equal to 760 torr. (1 micron = 1 millitorr, millitorr or microns = 1 torr, used as a measure of pressure).
Atomic Force Microscope (AFM): Atomic level surface mapping tool.
Autodoping: Dopant incorporated during the growth of an epitaxial layer from sources other than the dopant intentionally added to the vapor phase. Sources can include the back and front surfaces and edges of the substrate, and other substrates in the deposition assembly.

B

BESOI -- Bonded and Etch Back SOI
BGSOI -- Bonded and Grind Back SOI
BJT -- Bipolar Junction Transistor
BMD -- Bulk Micro-Defects or Bulk Microdefect Density (used almost exclusively as a measure of the oxygen precipitate density)
BOE -- Buffered Oxide Etch
BOX -- Buried Oxide Layer
BP -- Backside Polish
BV -- Breakdown Voltage
Bvox -- Breakdown Voltage-oxide
Backside: Side of the wafer that is NOT going to be polished. It is the side where the Enhanced Getter layer and/or LTO layer is placed if specified by the customer.
Backside OSF: Mechanical damage on the backside of the wafer that can precipitate stacking fault defects for gettering of impurities.
Baffle: Wafer or quartz used in furnaces to break course of gas flow at product wafers.
BDD: Bulk defect density.
BMD: Bulk Micro Defect.
Bonded Wafer: Two wafers bonded together: see SOI.
Bow: Bend or concavity of the wafer/slice. A measure of the lack of flatness of the wafer/slice.
BOX: Buried Oxide layer on SOI wafer.
Box-And-Whisker: Charting tool that visualizes data on a graph: the mean, middle 2 quartiles (50%), the upper (25%) and lower (25%) quartiles, and the largest and smallest values.
BSD: Backside damage, a process of mechanically damaging the backside of a wafer to increase gettering.
Bulk Precipitation: Defects in silicon used for gettering of impurities and can include dislocation loops, stacking fault defects, and oxygen precipitate defects.
Buried Layer: A diffused region that is covered with an epitaxial layer, subdiffused layer, or a diffusion under film.
Bvox: Breakdown voltage test of oxide layer grown on wafers, sister test to GOI.

C

oC -- Centigrade
oC/min -- Centigrade per minute
CD -- Critical Dimension
CE -- Caustic Etch
CIS -- CMOS Imaging System
cm-- Centimeter (0.01 meter)
CMOS -- Complementary Metal Oxide Semiconductor
CMP -- Chemical Mechanical Polishing
CO -- Carbon Monoxide
CO -- Carbon Dioxide
COO -- Cost of Ownership
COP's -- Crystal Originated Particles
CoQC -- Certificate Of Quality Conformance
CP -- Crystal Puller
CTL -- Charge Trap Layer
CV -- Capacity or capacitance voltage
CVD -- Chemical Vapor Deposition
CZ -- Czochralski method of pulling single crystal
Cantilever: Ceramic or silicon carbide rod or silicon carbide paddle that holds the quartz boats. This device is supported at one end. In this case, it is the door end and has the same function as a sled.
Capability Index: Value to measure how capable a product or process is at meeting a specification.
Carbon Beam: Length of carbon approximately 2" wide attached to the bottom of an ingot. In the slicing process the carbon allows the saw to cut completely through the silicon. The beam remains intact to hold the wafers until the preset number of wafers have been cut.
Carriers: Stainless steel apparatus used to contain wafers during the lapping process.
Cassette: Compact case designed to segregate slices for process handling and shipping.
Chamfer: Beveled edge.
Charge: Specified quantity of poly to be loaded into the crystal puller.
Cleanroom: Controlled areas with a low particle size/count where the latter part of wafer production takes place. The below table shows how classes are defined, with class 1 being the cleanest environment.
Class: # of particles allowed in a cubic foot of room air Particle Size
1 (means it can have no more than 1 particle) 0.5 micron or greater
10 0.5 micron or greater
100 (means it can have no more than 100 particles) 0.5 micron or greater
0.5 micron or greater
10,000 0.5 micron or greater
Cleavage Plane: A break along crystal planes determined by crystal structure and always parallel to such a plane.
CMP: (Chemical-Mechical Polish) A process of removing surface material using chemical and mechanical means to achieve a mirror-like surface in preparation for subsequent processing.
Collimated Light: Light source in which the rays are parallel. Used for surface inspection of wafers.
Conductivity: A measure of the ease with which electrical carriers flow in a material: the reciprocal of Resistivity.
Conductivity Type: Defines the nature of the majority of carriers in the material: either N-type or P-type.
Contamination: Foreign matter in the silicon, other than polysilicon and dopant, that can cause loss of structure (atom alignment) during the growing process.
COP: Crystal Originated Pits.
Cp: Capability potential index which measures the width of two specifications in respect to six standard deviations.
Cpk: Statistical parameter used to compare product distribution to spec limits. A capability potential index measuring the distance from the mean to the nearest specification in respect to three standard deviations.
Crucible: Container made of quartz for holding the poly charge inside the crystal puller.
Crystal: A natural or synthetic semiconductor material whose atoms are arranged with some degree of geometric regularity. A solid composed of atoms, ions, or molecules arranged in a pattern that is periodic in three dimensions.
Crystal Puller: Machine designed to pull/grow electronic grade silicon under controlled parameters and within set specifications.
Crystallographic Orientation: There are three orientation planes in the silicon crystal: <100>, <110>, and <111>. The orientation of the wafer is classified by which orientation plane the surface of the wafer is parallel to. The surface might not be exactly parallel, but slightly different, and the difference is called the displacement angle or off angle orientation. The relationship between the crystal's orientation and the radius is marked by either a notch or a flat cut into the wafer.
Cubic Feet per Minute (CFM): Volumetric flow rate used to meter gases.
CVD (Chemical Vapor Deposition): Formation of a solid film on a substrate through the reaction of gas-phase reactants (precursors) that contain the required constituents.
Czochralski (CZ): Crystal growing process that was named after the inventor.

D

D-defects -- Very small voids in Silicon formed by agglomeration of vacancies
DIBL -- Drain Induced Barrier Lowering
DIC -- Differential Interference Contrast
DL -- Diffusion Length
DMOS -- Double-diffused MOS
DOE -- Design of Experiments
DOF -- Depth of Focus
DRAM -- Dynamic Random Access Memory
DSOD - Direct Surface Oxide Defect
DSP -- Double Sided Polish
DZ -- Denuded Zone (depth measured from the surface that is free of oxygen precipitates and which is denuded of interstitial oxygen (by out-diffusion))
Defect Free Region: The linear distance from the frontside wafer surface to the depth of the first bulk defect.
Degree: Unit of measuring angles when orienting an ingot.
Design of Experiments (DOE): Method to design, run and analyze an experiment to maximize information and minimize testing.
Diameter: Straight-line measurement drawn through the center of a circle or sphere from one side to the other.
Diffusion: A method of doping or modifying the characteristics of semiconductor material by "baking" wafers of the base semiconductor material in furnaces with controlled atmospheres of impurity materials.
Diffusion Length: The distance a front side free-electron or hole can travel through a crystal. This is proportional to the Lifetime of the crystal.
Dislocation: A class of one-dimensional, or line defects in silicon crystals.
DNZ (Denuded Zone Depth): The linear distance from the frontside wafer surface to the depth where the defect density appears nearly uniform.
Donor: Atom, usually an impurity in silicon, that acts as an electron source. It contributes an extra electron to the crystal structure. Most common is phosphorus.
Dopant: Element added to silicon decreasing its resistivity. Silicon, by itself does not conduct electricity. Boron is usually used for p-type and phosphorus is usually used for n-type.
Doping or Dopant: Chemical impurities added to polysilicon which will yield either n- or p-type silicon, depending on the specific dopant used.

E

eDRAM -- Embedded Dynamic Random Access Memory
EG -- Enhanced Gettering
EEPROM -- Electrically-erasable and Programmable Read-only Memory
EPROM -- Erasable and Programmable Read-only Memory
EOT -- Equivalent Oxide Thickness
EPI -- Epitaxy
ESF -- Epi Stacking Fault
Edge Crown: The difference between the surface elevation 1/8" (3.2mm) from the edge of the slice and the elevation of the slice edges exposed in microns (associated with epi layer deposition).
Edge Exclusion: Narrow band on the outside edge of the wafer that does not have an oxide coating.
Edge Grinding: Process that bevels the edges of the slices to strengthen them.
Ellipsometer: Optical measuring device used to measure oxide and nitride thickness, as well as, the index of refraction.
Epi: (epitaxial or epitaxy process) Depositing a thin layer of silicon atoms onto a wafer by condensing a controlled amount of silicon gas (silane) onto the polished surface of the wafer in a temperature-controlled environment.
Epitaxial Layer: The layer or layers of semiconductor material having the same crystalline orientation as the host substrate on which it is grown.
Endcone or Bottom: Gradual decreases in diameter until the silicon forms a point at the end of the growing/pulling process. As a rule of thumb, the bottom/endcone should be grown the length of the rod's diameter to allow for shock back or undesirable structure.
Etch: To remove or dissolve surface contamination, work-damaged material (polishing), and to control thickness by chemical action with strong acid and alkaline compounds.
Etch - Mirror: Used to create a clean, shiny finish for visual inspection and resistivity measurements.
Etch - Preferential: An etch that exhibits an accelerated etch rate along specific crystallographic planes.
Etch Rate: Rate of silicon removal in microns per minute.

F

FBE -- Floating Body Effect
FET -- Field Effect Transistor
FD-SOI -- Fully Depleted Silicon-on-Insulator
FPD -- Flow Pattern Defect (ref. Crystal)
FPD -- Focal Plane Deviation (ref. Mechanical flatness)
FRAM -- Ferroelectric Random Access Memory
FTIR -- Fourier Transform Infra-Red Spectroscopy
FZ -- Float Zone method of Crystal Pulling
Face: Parallel lines along the surface of the crystal, also known as growth lines or ZD, zero defect, lines.
Flat: Straight edge on the wafer's outer perimeter. It is used to identify certain characteristics. (AKA the JLS).
Flat (major): May be the only flat (straight edge) on the wafer. If there is more than one flat then it is the longest flat on the perimeter of the wafer.
Flat (minor): Shortest flat (straight edge) on the wafer.
Flatness: The maximum deviation of the wafer surface from a flat plane. Flatness measurement is usually done with the backside held to a flat surface (a vacuum chuck) and excludes linear thickness variations.
Focal Plane: That plane whose normal provides the shortest distance between the absolute maximum and absolute minimum on the wafer surface.
Focal Plane Deviation (FPD): Maximum deviation of the wafer surface above and below the focal plane.
FTIR: Fourier Transform Infrared, a means of measuring oxygen or carbon levels in the crystal.

S

SAC -- Submicron Application Crystal
SBIR -- Site flatness, back-referenced
SBSD -- Soft Backside Damage
SC1 -- 1st cleaning bath in the standard "RCA clean" sequence, consisting of NH4OH / H202/ H20 solution designed to remove particles from Si surface
SC2 -- 2nd cleaning bath in the standard "RCA clean" sequence, consisting of HCl / H202/ H20 solution designed to remove metals from Si surface
SCE -- Short Channel Effects
SEM -- Scanning Electron Microscope
SFQR -- Site flatness, best-fit, front-referenced
SFSR -- Site flatness, best-fit, front-referenced, scanning site
SGOI - Strained Si on SiGe on Insulator
Si -- Silicon
SIE -- Square Inch Equivalent
SIMOX -- Separation by Implantation of Oxygen
SIMS -- Secondary Ion Mass Spectroscopy
SiO -- Silicon Monoxide
SiO2 -- Silicon Dioxide
SIP -- Single In-line Package
SIRM -- Scanning Infra-red Microscope
SoC -- System-on-a-Chip
SOI -- Silicon-on-Insulator
SOS -- Silicon-on-Sapphire
SPT -- Soft Punch Through
SPV -- Surface Photovoltage
SRAM -- Static Random Access Memory
SRP -- Spreading Resistance Probe or Spreading Resistance Profile
SSI -- Small-scale Integration
sSi -- Strained Silicon
SSIS -- Surface Scanning Inspection System
SSOI -- Strained Silicon directly on Insulator
SSP -- Single Side Polish
STD -- Standard
STD CZ -- Standard Czochralski-grown Crystal
STI -- Shallow Trench Isolation
STIR -- Site TIR (Total Indicated Reading)
Secondary Ion Mass Spectrometry (SIMS): Dopant and impurity depth profiling, done by outside vendors for SunEdison Semiconductor.
Seed End (SE): Beginning end of a grown silicon crystal rod.
Seed Crystal: The seed is the starting point for growing the ingot. It must have the same crystal orientation as desired for the resulting ingot.
SEMI: Semiconductor Equipment and Materials Institute. Sets specifications for the semiconductor industry.
Silicon: Tetravalent nonmetallic element that occurs combined as the most abundant element next to oxygen in the earth's crust and is used in alloys and electronic devices.
Single Crystal: When the atoms in the crystal are all aligned in the same way.
Slip: A process of plastic deformation in which one part of the crystal undergoes a shear displacement relative to another in a fashion that preserves the crystallinity of the material. The direction is on a specific crystallographic plane.
Slug: Thick piece of silicon, usually a wedge cut, used to test the material characteristics for customer specs.
Slurry: Solid suspension in liquid used for slicing, lapping, and polishing.
SOI: Silicon on Insulator, usually achieved by bonding two wafers, one of which has oxide on top.
SRP - Spreading Resistance Profiling: The resistance measured between the conductive metal of a point probe and a large area, relatively low-resistance semiconductor contact, dominated by the resistivity of the semiconductor volume close to the problem.
Stacking Faults: Pyramid shaped imperfections in the silicon wafer.
Substrate: Basic surface on which a material adheres. A single-crystal slice that is the basis for subsequent processing operations, such as epi layer deposition, diffusion, ion implants, etc.
Surface Photovoltage (SPV): Test for recombination minority carrier lifetime.
Swirl: Shallow pits looked for during visual inspection. Helical or concentric features that are visible to the unaided eye after preferential etch, and appear to be discontinuous under 150x magnification.

T

T -- Temperature
TCS -- Trichlorosilane
TEM -- Transmission Electron Microscope
TIR -- Total Indicated Reading
TOX -- Gate Oxide Thickness
Tsoi -- Thickness of SOI top Si layer
TSOP -- Thin Small Outline Package
TTV -- Total Thickness Variation
Taper: A measure of the flatness of a wafer, taper being thicker at the edges than at the center.
Thickness: Cross sectional depth of a silicon slice measured in mils (1 mil = 0.001 inch).
TIR: Total Indicator Reading, the distance between the highest and lowest point on the wafer surface measured normal to the focal plane.
Total Thickness Variation (TTV): variation of thickness from the center and both sides of the wafer.

U

ULSI-- Ultra Large-scale Integration

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